DocumentCode
237694
Title
A novel transient fault injection technique using Berlekamp-Massey Algorithm
Author
Khuntia, Ashirbad ; Sasamal, Trailokya Nath
Author_Institution
Sch. of VLSI Design & Embedded Syst. Design, NIT Kurukshetra, Kurukshetra, India
fYear
2014
fDate
8-10 May 2014
Firstpage
541
Lastpage
545
Abstract
Designing of a reliable digital system is a challenging task because it incorporates testing of circuits at the design time. With this feature the designer can depict testable circuit for transient faults at the design stage. In this paper we have proposed a technique of transient fault injection system with the help of Verilog description based language. The key feature of the fault injection system is pseudo random sequence which is generated through LFSR. Standard LFSR based fault injection system is less efficient in terms of hardware utilization; to reduce hardware of the injection system Berlekamp-Massey Algorithm (BMA) is used. Experimental results show that the proposed technique has a superior performance, compared to existing technique.
Keywords
electronic engineering computing; fault tolerance; hardware description languages; integrated circuit design; integrated circuit testing; random sequences; shift registers; BMA; Berlekamp-Massey algorithm; Verilog description based language; design time; pseudo random sequence; reliable digital system; standard LFSR based fault injection system; testable circuit; transient fault injection technique; Hardware; Hardware design languages; Logic gates; Registers; BIST; Berlekamp Massey algorithm; LFSR; Transient Fault; Verilog;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on
Conference_Location
Ramanathapuram
Print_ISBN
978-1-4799-3913-8
Type
conf
DOI
10.1109/ICACCCT.2014.7019144
Filename
7019144
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