MOSFET sub-threshold current reduction by varying substrate doping

This paper presents a technique to reduce the sub-threshold current in MOSFET by changing the doping profile in the substrate region near the channel. Sub-threshold current is also known as drain leakage current. The size of MOSFET can be reduced but at the cost of increase in leakage of current from drain to source in its stand by mode. This leakage current dissipates power even if the device is not in use. To avoid this problem leakage must be reduced so that the advantage of reduced size may be tapped more efficiently. The results have been observed using 180nm, 90nm, 45nm, 32nm MOSFET technology. The simulated results clearly show that there is a considerably large reduction in sub-threshold current with a change in acceptor doping concentration from 2.50e + 17 cm^-3 to 5.00e + 18 cm^-3 to of the channel region in the substrate.