A 19.1-dBm Fully-Integrated 24 GHz Power Amplifier Using 0.18-μm CMOS Technology

Author

Kuo, Jing-Lin ; Tsai, Zuo-Min ; Wang, Huei

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2008

fDate

27-31 Oct. 2008

Firstpage

1425

Lastpage

1428

Abstract

A 24 GHz, 19.1 dBm fully-integrated power amplifiers (PA) was designed and fabricated in the 0.18-iquestm deep n-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration and has a maximum measured output power of 19.1 dBm, an OP_1dB of 13.3 dBm, a power added efficiency (PAE) of 15.6%, and a linear gain of 18.8 dB when V_DD and DNW are both biased at 3.6 V. The chip size is only 0.56 times 0.58 mm². To the author´s knowledge, this PA demonstrates the highest output power of +19.1 dBm among the reported PAs above 15 GHz in CMOS processes.

Keywords

CMOS integrated circuits; integrated circuit design; integrated circuit manufacture; power amplifiers; radiofrequency integrated circuits; CMOS processes; VDD; cascode RF NMOS configuration; deep n-well CMOS technology; frequency 15 GHz; frequency 24 GHz; gain 18.8 dB; linear gain; power added efficiency; power amplifier; voltage 3.6 V; CMOS technology; Gain measurement; MOS devices; Power amplifiers; Power generation; Power measurement; Radio frequency; Radiofrequency amplifiers; Semiconductor device measurement; Size measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2008. EuMC 2008. 38th European

Conference_Location

Amsterdam

Print_ISBN

978-2-87487-006-4

Type

conf

DOI

10.1109/EUMC.2008.4751733

Filename

4751733