HIVE: an express and accurate interconnect capacitance extractor for submicron multilevel conductor systems

This paper presents a new paradigm for fast and accurate 2-D and 3-D interconnect capacitance extraction suitable for sub-micron, multi-level (SMML) conductor systems. According to SMML interconnect process measurements and simulations, there are linear as well as nonlinear changes of area, fringing, and coupling capacitances when the interconnect pitch changes. A set of representative SMML layout structures are selected so that rigorous 2-D and 3-D simulations are done in advance for the nonlinear changes and fast interpolations/extrapolations are done for the linear changes. In this way, efficient and comprehensive capacitance curves can be generated to support VLSI designs. The average time spent on displaying the capacitance design curves on an X-window-based workstation is 1.4 seconds. The maximal difference between the interpolation/extrapolation results and the 2-D/3-D simulation results is within 3%