Development of a fail-safe microprocessor LSI with self-diagnosis mechanism depending on an M-sequence code signature

A bus-level synchronized computer system is widely utilized in the field of railway signaling in Japan. It may be recognized that there is a problem of disadvantage in manufacturing cost reduction. We intend to integrate a bus-level synchronized FS (fail-safe) computer into an LSI chip, in expectation of cost reduction and performance enhancement. An economical FS one-chip computer utilizing system LSI technology is realized. It assures fail-safety by means of a novel fault diagnosis mechanism depending on an M-sequence code signature. These techniques are reported in detail