Finding a small set of longest testable paths that cover every gate

Testing the longest path passing through each gate is important to detect small localized delay defects at a gate, e.g. resistive opens or resistive shorts. In this paper we present ATPG techniques to automatically determine the longest testable path passing through a gate or wire in the circuit without first listing all long paths passing through it. This technique is based on a graph traversal algorithm that can traverse all paths of a given length in a weighted directed acyclic graph. Experimental results for ISCAS benchmarks are also presented.