Title :
Improving SAT-based Combinational Equivalence Checking through circuit preprocessing
Author :
Andrade, Fabrício Vivas ; Silva, Leandro M. ; Fernandes, Antônio O.
Author_Institution :
Comput. Sci. Dept., Centro Fed. de Educ. Tecnol., Belo Horizonte
Abstract :
This paper presents a new implication tool (Vimplic) which can be used to improve SAT-based combinational equivalence checking. This tool quickly builds the implication graph of the miter circuit and traverse through it inferring implications among its nodes assignments. This set of implications and the miter circuit netlist are converted to conjunctive normal form (CNF) and submitted to the SAT solver in order to prove equivalence between the two circuits of the miter. Using Vimplic we have been able to dramatically reduce the overall verification time of several circuits outperforming the state-of-the-art techniques for CEC such as Berkmin561, NiVER, and C-SAT.
Keywords :
electronic engineering computing; program verification; Berkmin561; SAT-based combinational equivalence checking; circuit preprocessing; conjunctive normal form; implication graph; implication tool; miter circuit netlist; verification time; Binary decision diagrams; Boolean functions; Business continuity; Computer science; Data structures; Digital circuits; Electronics industry; Engines; Formal verification; Product design;
Conference_Titel :
Computer Design, 2008. ICCD 2008. IEEE International Conference on
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
978-1-4244-2657-7
Electronic_ISBN :
1063-6404
DOI :
10.1109/ICCD.2008.4751838