Advanced real Traffic Light Controller system design using Cortex-M0 ip on FPGA

Traffic light system establishes a set of rules and instructions that drivers rely on to avert collisions and other difficulties using signs, lights and other devices [1]. Now a day Traffic Light Controller (TLC) is based on microcontrollers and microprocessors. These TLC have limitations due to use of pre-defined hardware, which functions according to the program that has been done. The major drawback of such TLC systems is that they do not have the flexibility of modification on the basis of real time necessity. FPGA has many advantages over microcontroller, some of these advantages are; the speed, number of input/output ports and performance which are all very important in TLC design, at the same time ASIC design is more expensive than FPGA [2]. The Cortex-M0 processor is 32 bit RISC (Reduced Instruction Set Computing) processor with very low gate count. The low gate count of the processor gives the advantage of low power consumption. Most of the TLCs implemented on FPGA are simple ones that have been implemented as examples of FSM. This paper concerned with an FPGA design implementation of a 24-hour advanced traffic light controller system based on congestion on the road intersection using Cortex-M0 in VHDL. The system has been successfully tested and implemented in hardware using Xilinx Spartan-3E FPGA. This system has many advantages over the exciting TLC.