• DocumentCode
    2379367
  • Title

    Test cost minimization through adaptive test development

  • Author

    Chen, Mingjing ; Orailoglu, Alex

  • Author_Institution
    CSE Dept., UC San Diego, La Jolla, CA
  • fYear
    2008
  • fDate
    12-15 Oct. 2008
  • Firstpage
    234
  • Lastpage
    239
  • Abstract
    The ever-increasing complexity of mixed-signal circuits imposes an increasingly complicated and comprehensive parametric test requirement, resulting in a highly lengthened manufacturing test phase. Attaining parametric test cost reduction with no test quality degradation constitutes a critical challenge during test development. The capability of parametric test data to capture systematic process variations engenders a highly accurate prediction of the efficiency of each test for a particular lot of chips even on the basis of a small quantity of characterized data. The predicted test efficiency further enables the adjustment of the test set and test order, leading to an early detection of faults. We explore such an adaptive strategy, by introducing a technique that prunes the test set based on a test correlation analysis. A test selection algorithm is proposed to identify the minimum set of tests that delivers a satisfactory defect coverage. A probabilistic measure that reflects the defect detection efficiency is used to order the test set so as to enhance the probability of an early detection of faulty chips. The test sequence is further optimized during the testing process by dynamically adjusting the initial test order to adapt to the local defect pattern fluctuations in the lot of chips under test. Experimental results show that the proposed technique delivers significant test time reductions while attaining higher test quality compared to previous adaptive test methodologies.
  • Keywords
    flaw detection; minimisation; mixed analogue-digital integrated circuits; adaptive test development; defect pattern fluctuations; fault detection; mixed-signal circuits; parametric test data; test correlation analysis; test cost minimization; test selection algorithm; Circuit faults; Circuit testing; Costs; Degradation; Fault detection; Fluctuations; Manufacturing; Minimization; Semiconductor device measurement; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2008. ICCD 2008. IEEE International Conference on
  • Conference_Location
    Lake Tahoe, CA
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4244-2657-7
  • Electronic_ISBN
    1063-6404
  • Type

    conf

  • DOI
    10.1109/ICCD.2008.4751867
  • Filename
    4751867