A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture

Author

Miyazaki, M. ; Kao, J. ; Chandrakasan, A.P.

Author_Institution

Microsystems Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

58

Abstract

The power dissipation of a digital circuit is minimized by simultaneous control of power supply voltage and body bias. The technique minimizes power dissipation for varying processing rates through dynamic adjustment of V/sub dd/ and V/sub tb/. A 16b MAC operates at 166 kHz and 14 nW at 175 mV V/sub dd/. A ring oscillator operates at 0.1 V.

Keywords

CMOS digital integrated circuits; digital signal processing chips; integrated circuit measurement; minimisation; multiplying circuits; oscillators; voltage control; 0.1 V; 14 nW; 16 bit; 166 kHz; 175 mV; MAC; adaptive supply voltage/body bias architecture; digital circuit; dynamic voltage adjustment; multiply-accumulate unit; power dissipation; power dissipation minimization technique; processing rates; ring oscillator; simultaneous power supply voltage/body bias control; triple-well CMOS technology; Adaptive control; CMOS technology; Circuits; Clocks; Dynamic voltage scaling; Frequency; MOS devices; Power dissipation; Table lookup; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992937

Filename

992937