Title :
A multiple-crystal interface PLL with VCO realignment to reduce phase noise
Author :
Sheng Ye ; Jansson, L. ; Galton, I.
Author_Institution :
California Univ., San Diego, La Jolla, CA, USA
Abstract :
A phase realignment technique is applied to a ring oscillator VCO in a 3 V 6.8 mW CMOS PLL that converts most of the popular crystal reference frequencies to a 32 MHz baseband clock and RF PLL reference. The peak in-band phase noise at 20 kHz offset is -102 dBc/Hz with the technique enabled, and -92 dBc/Hz with the technique disabled.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; phase noise; voltage-controlled oscillators; 3 V; 32 MHz; 6.8 mW; CMOS PLL; RF PLL reference; VCO realignment; baseband clock; crystal reference frequencies; multiple-crystal interface PLL; peak in-band phase noise; phase noise; ring oscillator VCO; Bandwidth; Frequency conversion; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Radio frequency; Ring oscillators; Transceivers; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992947
