Title :
Proceedings of International Conference on Computer Aided Design
Abstract :
The following topics were dealt with: technology mapping; interconnect characterisation and analysis; high performance routing synthesis; sequential circuit testing; formal verification; system design: synthesis and compilation; timing analysis; high level design; high performance circuit optimisation; circuit partitioning; ATPG; implication based logic synthesis; numerical simulation techniques; robust routing; BIST and DFT; yield and technology modelling; verification and fault tolerance; analog CAD and methodology; delay fault test; BDD applications and techniques; transmission line analysis; power and current modelling; mixed-signal testing; logic synthesis; system level optimisation and validation; and fault diagnosis
Keywords :
automatic testing; built-in self test; circuit layout CAD; integrated circuit interconnections; logic CAD; logic testing; ATPG; BIST; DFT; analog CAD; compilation; current modelling; delay fault test; fault tolerance; formal verification; high level design; high performance circuit optimisation; high performance routing synthesis; interconnect characterisation; logic synthesis; numerical simulation; robust routing; sequential circuit testing; system design; technology mapping; technology modelling; timing analysis; transmission line analysis;
Conference_Titel :
Parallel and Distributed Processing, 1996., Eighth IEEE Symposium on
Conference_Location :
New Orleans, LA, USA
Print_ISBN :
0-8186-7683-3
DOI :
10.1109/SPDP.1996.570392