DocumentCode :
2380788
Title :
Hybrid multiplierless FIR filter architecture based on NEDA
Author :
Tecpanecatl-Xihuit, J.Luis ; Aguilar-Ponce, Ruth M. ; Bayoumi, Magdy
Author_Institution :
The Center for Advanced Computer Studies University of Louisiana at Lafayette, LA 70504-3749, USA
fYear :
2007
fDate :
15-17 Oct. 2007
Firstpage :
316
Lastpage :
319
Abstract :
This paper presents new hybrid multiplierless finite impulse response (FIR) architecture based on New Distributed Arithmetic (NEDA). The hybrid structure is a trade off between direct form and transposed direct form that results in a reduction of the critical path and the size of the delays elements as well as the fan-out. While the multiplications involved in the hybrid structure are replaced by a butterfly adder tree. Compared with previous methods, our proposed architecture achieves an average of 20% less additions. Moreover, the design method is simple and achieves better results than previous methods.
Keywords :
Communication standards; Computer architecture; Delay; Digital arithmetic; Distributed computing; Energy consumption; Filter bank; Finite impulse response filter; Switches; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on
Conference_Location :
Atlanta, GA, USA
Print_ISBN :
978-1-4244-1710-0
Electronic_ISBN :
978-1-4244-1710-0
Type :
conf
DOI :
10.1109/VLSISOC.2007.4402521
Filename :
4402521
Link To Document :
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