Enhancing the input bandwidth of CMOS track and hold amplifiers

Author

Tretter, G. ; Fritsche, David ; Carta, C. ; Ellinger, F.

Author_Institution

Circuit Design & Network Theor., Dresden Univ. of Technol., Dresden, Germany

fYear

2014

fDate

16-18 June 2014

Firstpage

1

Lastpage

4

Abstract

This paper presents a method to increase the input bandwidth of switched capacitor (SC) track and hold amplifiers (THAs), which is particularly suitable for time-interleaved analog-to-digital converters (ADCs). With a simple model for the track and hold stage, it is shown that frequency compensation techniques at the input of the THA can substantially increase the bandwidth at the controlled cost of increased distortion. A design example shows a bandwidth increase of 60% for a THA in a 4-bit ADC.

Keywords

CMOS integrated circuits; analogue-digital conversion; sample and hold circuits; switched capacitor networks; CMOS track and hold amplifiers; analog-to-digital converters; frequency compensation techniques; input bandwidth; storage capacity 4 bit; switched capacitor; time-interleaved ADC; track and hold stage; Bandwidth; CMOS integrated circuits; Capacitors; Integrated circuit modeling; Resonant frequency; Semiconductor device modeling; Switching circuits; ADC; THA; input bandwidth; time interleaving ADC; track and hold amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwaves, Radar, and Wireless Communication (MIKON), 2014 20th International Conference on

Conference_Location

Gdansk

Print_ISBN

978-617-607-553-0

Type

conf

DOI

10.1109/MIKON.2014.6899972

Filename

6899972