Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier

Author

Bisoyi, Abhyarthana ; Baral, Mitu ; Senapati, Manoja Kumar

Author_Institution

Dept. of Electron. & Commun., Nat. Inst. of Sci. & Technol., Berhampur, India

fYear

2014

fDate

8-10 May 2014

Firstpage

1757

Lastpage

1760

Abstract

Binary multipliers and addresses are used in the design and development of Arithmetic Logic Unit (ALU), Digital Signal Processing (DSP) Processors, Multiply and Accumulate (MAC).The objective of this paper is to implement digital multipliers based on the concept of Vedic mathematics. In order to develop a digital multiplier, Urdhva-tiryakbyham sutra of Vedic mathematics is used to implement vertical and cross wise operations. Since these are digital multipliers, they are implemented on FPGA board and are tested through the 8 LED (s) in FPGA (Nexys 3). A 32-bit Vedic multiplier has been simulated in Xilinx ISE 13.4 and has been compared with a 32-bit binary multiplier.

Keywords

digital arithmetic; digital signal processing chips; field programmable gate arrays; integrated circuit testing; multiplying circuits; ALU; DSPprocessors; FPGA board; LED; MAC; Nexys 3; Urdhva-tiryakbyham sutra; Vedic mathematics; Vedic multiplier; Xilinx ISE 13.4; arithmetic logic unit; binary multiplier; digital multipliers; digital signal processing; field programmable gate arrays; multiply and accumulate; Field programmable gate arrays; Table lookup; FPGA; Vedic mathematics; Xilinx ISE; binary multipliers;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on

Conference_Location

Ramanathapuram

Print_ISBN

978-1-4799-3913-8

Type

conf

DOI

10.1109/ICACCCT.2014.7019410

Filename

7019410