Design of power efficient pseudorandom sequence generator using decimation

Generation of pseudo-random binary sequence with low power consumption and higher throughput rates is an issue of utmost importance in today´s electronics industry. The main challenging areas in VLSI Design are power consumption and higher throughput rates. Linear Feedback Shift Register (LFSR) designed with parallel architecture is capable to generate pseudo random binary sequence with low power consumption and higher throughput rate as compared to the conventional LFSR. Parallel architecture can be obtained by decimation which results in sub sequence generation of the original sequence at a faster rate as compared to the conventional LFSR. This paper presents a power efficient solution for pseudorandom sequence generator using the method of decimation. The effect of decimation on power consumption and throughput rate has been studied. This study has been carried out by varying the lengths of the generated sequence. Moreover, it has also been studied that how by changing the frequency of the clock generator the power consumption can be reduced in an LFSR employing decimation as compared to the conventional LFSR.