Title :
Fully understanding the mechanism of misalignment-induced narrow-transistor failure and carefully evaluating the misalignment-tolerant SRAM-cell layout
Author :
Nakai, Satoshi ; Miyazaki, Yasumori ; Nakamura, Ryo ; Suga, Masato ; Tsuruta, Tomoya ; Yasuda, Makoto ; Kashiwagi, Takamitsu ; Maki, Yasuhiko
Abstract :
We have demonstrated a misalignment-tolerant SRAM cell successfully, whose layout has been created from consideration of narrow-transistor failure through physical and electrical analyses. To evaluate an advantage of the layout, we have performed an intentionally misaligned experiment using a test structure with each SRAM block featuring a neighbor alignment-inspection mark.
Keywords :
SRAM chips; failure analysis; integrated circuit layout; transistors; SRAM block featuring; electrical analysis; misalignment-induced narrow-transistor failure; misalignment-tolerant SRAM-cell layout; narrow-transistor failure; neighbor alignment-inspection mark; physical analysis; test structure; Circuit testing; Etching; Failure analysis; Lithography; Microelectronics; Performance evaluation; Random access memory; SRAM chips; Shape; Very large scale integration; Failure analysis; Integrated circuit layout; SRAM chips;
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location :
Hiroshima
Print_ISBN :
978-1-4244-6912-3
Electronic_ISBN :
978-1-4244-6914-7
DOI :
10.1109/ICMTS.2010.5466834
