Title :
An Integrated Timing and Dynamic Supply Noise Verification Methodology for Nanometer CMOS SoC Designs
Author :
Shimazaki, Kenji ; Nagata, Makoto ; Sato, Kazuhiro
Author_Institution :
Matsushita Electr. Ind. Co., Ltd., Kyoto
Abstract :
A semi-dynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit noise; nanoelectronics; system-on-chip; built-in noise probing; dynamic drop; dynamic supply noise verification; dynamic timing analysis; large scale circuit; nanometer CMOS SoC design; on-chip delay monitoring; system-on-chip; CMOS logic circuits; Circuit noise; Circuit testing; Delay estimation; Integrated circuit noise; Logic design; Noise measurement; Power supplies; Timing; Voltage;
Conference_Titel :
Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on
Conference_Location :
Padova
Print_ISBN :
1-4244-0097-X
DOI :
10.1109/ICICDT.2006.220788
