A high data rate parallel demodulator suited to FPGA implementation

The architecture of high data-rate parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform is presented in this paper. The parallel architecture is based on frequency-domain implementation of matched filter and timing phase correction, which was first reported in Alternate Parallel Receiver (APRX). O&M timing error estimator based dual parallel feedback loop is proposed for timing recovery, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier recovery, their parallel implementation structures suitable for FPGA platform are also investigated. A demonstrate of 5 Gbps demodulator for 64 QAM modulation is given, fixed point simulation shows that this architecture can efficiently work with performance loss less than 1 dB.