VLSI implementation of a wormhole router using virtual channels

Presents the VLSI design of a router chip which implements wormhole routing using virtual channels. The router chip is intended for high-speed interconnection networks in parallel processors, and is capable of handling any interconnection network which is achieved by providing the routing function as a RAM-based lookup table. The architectural description of the chip is provided. The behavioral description of the chip is made by using the Verilog HDL. Finally, the chip is implemented using the standard-cell design automation package, OASIS