Title :
A scalable low power imager architecture for compound-eye vision sensors
Author :
Boussaid, Farid ; Shoushun, Chen ; Bermak, Amine
Author_Institution :
Sch. of Electr., Electron. & Comput. Eng., Western Australia Univ., Perth, WA, Australia
Abstract :
In this paper, we propose a scalable low power imager architecture for compound-eye vision sensors. The proposed hardware architecture is based on a time domain data representation as well as a biologically inspired read-out strategy using address-event-representation (AER). The proposed AER approach to compound-eye imaging enables low power operation (10nA/pixel), efficient read-out, improved signal-to-noise ratio together with wide dynamic range. Moreover, the proposed AER-based VLSI architecture is scalable and well suited to the next generation of deep submicron silicon processes owing to decreased supply voltage, process variability and increased noise levels.
Keywords :
CMOS image sensors; VLSI; integrated circuit design; low-power electronics; time-domain analysis; AER-based VLSI architecture; address-event-representation; compound-eye imaging; compound-eye vision sensor; deep submicron silicon process; hardware architecture; imager architecture; read-out strategy; signal-to-noise ratio; time domain data representation; wide dynamic range; Biosensors; Dynamic range; Dynamic voltage scaling; Hardware; Image sensors; Noise level; Pixel; Signal to noise ratio; Silicon; Very large scale integration;
Conference_Titel :
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Print_ISBN :
0-7695-2403-6
DOI :
10.1109/IWSOC.2005.26