Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

Author

Kinoshita, T. ; Hasumi, R. ; Hamaguchi, M. ; Miyashita, K. ; Komoda, T. ; Kinoshita, A. ; Koga, J. ; Adachi, K. ; Toyoshima, Y. ; Nakayama, T. ; Yamada, S. ; Matsuoka, F.

Author_Institution

Syst. LSI Div. I, Toshiba Corp., Yokohama

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The delay is enhanced to 21% at 0.8V for 3-input NAND gates. Energy delay product (EDP) is improved by more than 50% with DSS at 0.8V

Keywords

CMOS logic circuits; Schottky gate field effect transistors; logic gates; low-power electronics; 0.8 V; bulk CMOS logic circuits; constant standby current; dopant segregated Schottky source/drain transistors; energy delay product; multiple fan-in NAND gates; propagation delay; ultra low power circuit operation; ultra low voltage operations; CMOS logic circuits; CMOS technology; Decision support systems; FETs; Immune system; Large scale integration; Low voltage; MOSFETs; Propagation delay; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0439-8

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.346961

Filename

4154396