VHDL simulation and modeling of an all-digital RF transmitter

We describe a simulation technique that uses an event-driven VHDL simulator to model an RF wireless transmitter. The technique is well suited to investigate complex interactions in large SoC systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristics are described using time-domain equations. The flip-flop metastability effects on the system performance are also modeled. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a single-chip GSM/EDGE transceiver IC fabricated in a digital 90 nm process.