Enhancing performance and saving energy in CMOS DCVSL gates by using a new transistor sizing algorithm

Author

Masoumi, N. ; Ghasemi, J. ; Ahmadian, M. ; Raissi, F. ; Masoumi, Massoud

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

fYear

2005

fDate

20-24 July 2005

Firstpage

283

Lastpage

288

Abstract

In this paper we describe an algorithm for transistor sizing in CMOS DCVSL (differential cascode voltage switch logic) digital circuits. Our proposed method has two different approaches with low computational burden, mathematical based and genetic algorithm based. Using our transistor sizing algorithm, we minimized the propagation delay of a DCVSL full-adder and a DCVSL XOR in 0.5 μm CMOS technology. At first, the optimum sizes of these circuits were calculated to obtain the minimum propagation delay. Then the final transistor sizes were obtained by trading off speed, energy and area to meet a set of performance requirements.

Keywords

CMOS logic circuits; adders; genetic algorithms; logic design; logic gates; minimisation of switching nets; 0.5 micron; CMOS DCVSL gates; differential cascode voltage switch logic; digital circuits; genetic algorithm; propagation delay minimization; transistor sizing algorithm; CMOS logic circuits; CMOS technology; Circuit simulation; Energy consumption; Genetic algorithms; Integrated circuit noise; Mathematical model; Propagation delay; Semiconductor device modeling; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Print_ISBN

0-7695-2403-6

Type

conf

DOI

10.1109/IWSOC.2005.57

Filename

1530957