Tiled silicon: a packaging alternative to large silicon chips

Recent advances in area array chip bonding combined with the availability of high density substrates facilitate novel approaches to partitioning future systems. We examine one such new paradigm here: tiled silicon, in which system integration is achieved by tiling a set of chips together using area bonding on high density substrates rather than by pursuing single chip integration. We simulate the partitioning of large Si/CMOS chips into tiled arrays of silicon chips, including in the analysis wiring lengths, electrical interconnect issues, I/O requirements, including drivers and electrostatic damage (ESD) protection, wiring capacity, floorplans, wiring demand, escape, manufacturing yield, cost, and other electrical and thermal issues. Partitions are assumed to be interconnected via random logic, bus or memory type net topologies. Our results clearly show that it is possible to effectively tile silicon chips, when they are connected by reduced Rent exponent random logic, busses, or memory type net topologies. Systems with high interconnect demand, and thus little or no functional integration, cannot be tiled because of problems with larger chip real estate for drivers for off-chip lines and driver chip I/O escape