• DocumentCode
    2391478
  • Title

    An area-efficient high-speed AES S-box method

  • Author

    Hobson, Richard ; Wakelin, Scott

  • Author_Institution
    Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
  • fYear
    2005
  • fDate
    20-24 July 2005
  • Firstpage
    376
  • Lastpage
    379
  • Abstract
    The advanced encryption standard makes repeated use of a performance limiting randomization step, SubBytes, which invokes an S-box logic junction to scramble 8 data inputs. This paper introduces a new method for implementing S-box (and a variant, called T-box) logic functions. The method is as fast as previous methods, but uses only one quarter of the gates of other fast methods. In addition, the method can produce a differential output which helps to speed up downstream exclusive-or logic.
  • Keywords
    cryptography; logic design; logic gates; AES S-box method; SubBytes; advanced encryption standard; differential output; exclusive-or logic; logic junction; Binary decision diagrams; Boolean functions; Cryptography; Data engineering; Data structures; Delay; Field programmable gate arrays; Galois fields; Logic functions; Minimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
  • Print_ISBN
    0-7695-2403-6
  • Type

    conf

  • DOI
    10.1109/IWSOC.2005.37
  • Filename
    1530975