An FPGA based accelerator for SAT based combinational equivalence checking

Author

Safar, Mona ; El-Kharashi, M. Watheq ; Salem, Ashraf

Author_Institution

Dept. of Comput. & Syst. Eng., Ain Shams Univ., Cairo, Egypt

fYear

2005

fDate

20-24 July 2005

Firstpage

419

Lastpage

424

Abstract

In this paper we present software/reconfigurable hardware SAT accelerator for combinational equivalence checking. The SAT binary clauses are mapped into an implication graph and the ternary clauses are kept in an indexed clause database and mapped into the clause evaluator and conflict detector implemented on FPGA. The validity of the proposed approach is shown through the ISCAS´85 benchmark circuits.

Keywords

combinatorial mathematics; computability; field programmable gate arrays; reconfigurable architectures; binary clauses; clause evaluator; combinational equivalence checking; conflict detector; field programmable gate arrays; implication graph; indexed clause database; software/reconfigurable hardware SAT accelerator; ternary clauses; Binary decision diagrams; Business continuity; Computer graphics; Concurrent computing; Databases; Detectors; Engines; Field programmable gate arrays; Hardware; Reconfigurable logic;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Print_ISBN

0-7695-2403-6

Type

conf

DOI

10.1109/IWSOC.2005.40

Filename

1530983

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2391665