Performance improvement of configurable processor architectures using a variable clock period

Programmable and configurable processors are becoming increasingly popular for embedded wearable devices. In configurable processors technology it is a common practice to define specialized instructions in order to boost the performance of the device. These instructions may not fit in a single clock period and therefore, may require two clock periods for completion of a given task. In the past, we have proposed a method to generate a clock where each cycle can have a different length, and in this paper we investigate the performance gain it can give compared to standard clocking. Using our variable fractional clock period method, a gain of more than 10% in performance is easily obtained, with a maximum of 21%, compared to current best clocking techniques used in extensible configurable processors. We also show that the overall speedup of our method follows the well known Amdahl´s law, but without quantization of the acceleration factor.