DocumentCode
2391872
Title
Simulation and analysis of network on chip architecture for wireless communication system
Author
Yoon, Sung-Rok ; Park, Sin-Chong
Author_Institution
Inf. & Commun. Univ., Daejeon, South Korea
fYear
2005
fDate
20-24 July 2005
Firstpage
471
Lastpage
475
Abstract
In this paper, analysis of NoC architecture through consideration of the characteristics of wireless communication system is introduced. In this analysis, two constraint equations are used to evaluate whether the architecture is suitable for wireless communication system. In addition, a case study that applies the IEEE 802.11a in order to estimate the required number of processors is included. According to the case study, we also simulate the minimum required frequencies and buffer sizes of switches and processors.
Keywords
IEEE standards; integrated circuit design; mobile communication; system-on-chip; wireless LAN; IEEE 802.11a; network on chip architecture; processor buffer size; switch buffer size; wireless communication system; Analytical models; Communication switching; Equations; Frequency; Information analysis; Network-on-a-chip; Packet switching; Switches; Time to market; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Print_ISBN
0-7695-2403-6
Type
conf
DOI
10.1109/IWSOC.2005.98
Filename
1530993
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