• DocumentCode
    2392092
  • Title

    A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization

  • Author

    Kawashima, Junya ; Ochi, Hiroyuki ; Tsutsui, Hiroshi ; Sato, Takashi

  • Author_Institution
    Grad. Sch. of Inf., Kyoto Univ., Kyoto, Japan
  • fYear
    2011
  • fDate
    26-28 Sept. 2011
  • Firstpage
    57
  • Lastpage
    62
  • Abstract
    This paper investigates a design strategy for sub-threshold circuits focusing on energy-consumption minimization and yield maximization under process variations. It is shown that 1) the minimum operation voltage (VDDmin) of a circuit is dominated by FFs, and it can be improved by appropriate transistor sizing, 2) VDDmin of a FF is stochastically modeled by a log-normal distribution, 3) VDDmin of a large circuit can be estimated using the above model without extensive Monte-Carlo simulations, and 4) improving VDDmin may substantially contribute to reduce energy consumption.
  • Keywords
    flip-flops; logic design; DCT circuit; discrete cosine transform circuit; energy-minimization; extensive Monte-Carlo simulations; flip-flops; log-normal distribution; subthreshold circuit design strategy; transistor sizing; yield-maximization; Circuit simulation; Discrete cosine transforms; Energy consumption; Integrated circuit modeling; Logic gates; Threshold voltage; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference (SOCC), 2011 IEEE International
  • Conference_Location
    Taipei
  • ISSN
    2164-1676
  • Print_ISBN
    978-1-4577-1616-4
  • Electronic_ISBN
    2164-1676
  • Type

    conf

  • DOI
    10.1109/SOCC.2011.6085076
  • Filename
    6085076