A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow

As VLSI technology pushes into advanced nodes, designers and foundries have exposed a hitherto insignificant set of yield problems. To combat yield failures, the semiconductor industry has deployed new tools and methodologies commonly referred to as design for manufacturing (DFM). Most of the early efforts concentrated on catastrophic failures, or physical DFM problems. Recently, there has been an increased emphasis on parametric yield issues, referred to as electrical-DFM (e-DFM). In this paper, we present a complete electrical-aware design for manufacturing solution that detects, analyzes, and fixes electrical hotspots (e-hotspots) caused by different process variations within the analog circuit design. Novel algorithms are proposed to implement the engines that are used to develop this solution. Our proposed flow is examined on a 65nm industrial voltage control oscillator (VCO). E-hotspot devices with 5.5% variation in DC current are identified. After fixing the e-hotspots, the DC current variation in these devices is reduced to 0.9%, while saving the original VCO specifications.