Title :
PVT variations aware optimal sleep vector determination of dual VT domino OR circuits
Author :
Gong, Na ; Wang, Jinhui ; Sridhar, Ramalingam
Author_Institution :
State Univ. of New York, Univ. at Buffalo, Buffalo, NY, USA
Abstract :
In this paper, determining optimal leakage vector for dual Vt domino OR circuits is explored under process, supply voltage, and temperature (PVT) variations based on 65 nm bulk and 45 nm high k/metal gate (HK+MG) technologies, while considering design parameters, environmental parameters, working characteristics of circuits, and application cases. It concludes that the high clock signal with high inputs (CHIH) vector is the optimal sleep vector for practical low leakage register files applications, and the HK+MG technology further highlights the effectiveness of the CHIH vector as compared to other vectors.
Keywords :
logic gates; CHIH vector; PVT variations aware optimal sleep vector determination; dual VT domino OR circuits; high clock signal; high inputs vector; low leakage register files application; optimal leakage vector; temperature variation; Leakage current; Logic gates; MOS devices; Registers; Robustness; Transistors; Vectors;
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085092
