DocumentCode
2392860
Title
Eighth IEEE International High-Level Design Validation and Test Workshop
fYear
2003
fDate
12-14 Nov. 2003
Abstract
The following topics are dealt with: nano, quantum and molecular computing; processor validation and test; high-level design transformations; SAT and applications; system-level issues; functional vector generation and coverage; advances in sequential verification; behavioral/system-level test case generation; simulation-based verification.
Keywords
circuit simulation; computability; fault simulation; formal verification; high level synthesis; logic testing; molecular electronics; program testing; quantum computing; reliability; SAT solvers; fault injection; high-level design transformations; high-level design validation; high-level test; molecular computing; nano computing; processor test; processor validation; quantum computing; reliability; simulation-based verification;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-8236-6
Type
conf
DOI
10.1109/HLDVT.2003.1252466
Filename
1252466
Link To Document