Design of a neural recording amplifier with tunable pseudo resistors

Author

Yao, Kai-Wen ; Gong, Cihun-Siyong Alex ; Yang, Shan-Ci ; Shiue, Muh-Tian

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2011

fDate

26-28 Sept. 2011

Firstpage

376

Lastpage

379

Abstract

This paper describes a voltage-controlled pseudo-resistor with widely available operating voltage range applied to neural recording amplifier designs. The proposed pseudo-resistor which consists of serial-connected PMOS device and an auto-tuning circuit provides ultra-high resistance to cancel DC offset from electrode-electrolyte interface. The proposed design has been estimated in standard CMOS 0.18-μm process, achieving midband gain of 40 dB, bandwidth from 0.4 Hz to 7 kHz, input-referred noise of 5.98 μVrms, calculated NEF of 7.2, and 3.1-μW power consumption.

Keywords

MOS integrated circuits; amplifiers; neural chips; resistors; auto-tuning circuit; bandwidth 0.4 Hz to 7 kHz; electrode-electrolyte interface; gain 40 dB; neural recording amplifier; power 3.1 muW; serial-connected PMOS device; size 0.18 mum; tunable pseudo resistors; ultra-high resistance; voltage range; voltage-controlled pseudo-resistor; Bandwidth; CMOS integrated circuits; Cutoff frequency; Gain; Immune system; Noise; Resistors;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference (SOCC), 2011 IEEE International

Conference_Location

Taipei

ISSN

2164-1676

Print_ISBN

978-1-4577-1616-4

Electronic_ISBN

2164-1676

Type

conf

DOI

10.1109/SOCC.2011.6085119

Filename

6085119