DocumentCode
2393055
Title
A SAR ADC BIST for simplified linearity test
Author
Chao, An-Sheng ; Chang, Soon-Jyh ; Ting, Hsin-Wen
Author_Institution
Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2011
fDate
26-28 Sept. 2011
Firstpage
146
Lastpage
149
Abstract
A built-in self-test (BIST) scheme to quickly estimate differential nonlinearity (DNL) is proposed. The proposed scheme detects serious code deviation and reduces needed samples. Compared with the conventional code density test, the scheme reduces 97% sample count for a 10-bit approximation register analog-to-digital converters (SAR ADC).
Keywords
analogue-digital conversion; built-in self test; DNL estimation; SAR ADC BIST; analog-to-digital converters; approximation register; built-in self-test scheme; code density test; differential nonlinearity estimation; serious code deviation detection; simplified linearity test; successive approximation register; word length 10 bit; Built-in self-test; Capacitors; Linearity; Switches; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference (SOCC), 2011 IEEE International
Conference_Location
Taipei
ISSN
2164-1676
Print_ISBN
978-1-4577-1616-4
Electronic_ISBN
2164-1676
Type
conf
DOI
10.1109/SOCC.2011.6085122
Filename
6085122
Link To Document