Title :
Ultra low power QC-LDPC decoder with high parallelism
Author :
Cui, Ying ; Peng, Xiao ; Chen, Zhixiang ; Zhao, Xiongxin ; Lu, Yichao ; Zhou, Dajiang ; Goto, Satoshi
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
Abstract :
This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 8~16 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5× higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.
Keywords :
WiMax; cyclic codes; message passing; parity check codes; turbo codes; QC LDPC decoder; TDMP algorithm; WiMAX; low density parity check codes; parallel decoder architecture; quasi-cyclic codes; turbo decoding message passing; Clocks; Decoding; Hardware; Logic gates; Parallel architectures; Parallel processing; Parity check codes;
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085136