Title :
Complementary hybrid architecture with two different processing elements with different grain size
Author :
Hiraki, Kei ; Matsumoto, Takashi
Author_Institution :
Dept. of Inf. Sci., Tokyo Univ., Japan
Abstract :
In this paper, a basic architecture for efficient massively-parallel processing is discussed. In order to construct general-purpose massively parallel processing systems, efficient and close interaction between processing elements is the most critical issue. We propose a complementary processor architecture with two different processing elements which are optimized to different grain sizes (fine-grain and coarse-grain). The proposed architecture can exploit high performance of coarse-grained RISC processor performance in connection with flexible fine-grained operation such as distributed shared memory, versatile synchronization and message communications. After detailed discussion we describe the architecture of the prototype machine (JUMP-1)
Keywords :
distributed memory systems; optimisation; parallel architectures; parallel machines; reduced instruction set computing; shared memory systems; JUMP-1; coarse-grain; coarse-grained RISC processor; distributed shared memory; fine-grain; flexible fine-grained operation; grain size; high performance; hybrid architecture; massively-parallel processing; message communications; optimization; processing elements; prototype machine; versatile synchronization; Computer architecture; Grain size; Information science; Memory architecture; Optimizing compilers; Power system protection; Protocols; Prototypes; Reduced instruction set computing; Switches;
Conference_Titel :
TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: Frontiers of Computer Technology. Proceedings of 1994
Print_ISBN :
0-7803-1862-5
DOI :
10.1109/TENCON.1994.369284