22-nm damascene gate MOSFET fabrication with 0.9 nm EOT and local channel implantation

We have introduced a novel CMOS transistor fabrication technique using damascene gate with local channel implantation. This transistor has a benefit to reduce the resistance of source/drain extension without severe blanket channel implantation that causes large junction capacitance as well. Reliable process technologies were developed for the formation of channel length down to 22 nm. Gate patterns have no bumpy edges. Some new important processes for the fabrication of these small transistors are also introduced. Physical thickness of gate oxide was 0.9 nm with RTO. The 22 nm nMOSFETs are achieved with a drive current of 500 μA/μm for an off current of 100 nA/μm at 1.0V. We obtained the hot carrier reliability exceeding 10 years for 1.0V operation.