A fractional frequency synthesizer based on ADPLL

Author

Tsai, Chia-Chun ; Wu, Hsu-Heng ; Lee, Wen-Ta

Author_Institution

Inst. of Comput., Nat. Taipei Univ. of Technol., Taiwan

fYear

2003

fDate

6-8 Oct. 2003

Firstpage

151

Lastpage

154

Abstract

In this paper, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A new phase frequency acquisition mode is involved with an initial half-step size to speed up the convergence in phase and frequency comparisons. The dual modulus frequency divider by four or five is applied to perform the various fractions. The frequency synthesizer is implemented with TSMC 0.35 μm 1p4m CMOS technology. Experimental simulations show the more encourage results. The chip area is lower to 1.3 × 1.3 mm², locked time is less than 20 reference cycles, power consumption is only 15 mW, and the jitter is 90ps at 300 MHz.

Keywords

CMOS integrated circuits; digital phase locked loops; frequency dividers; frequency synthesizers; jitter; 15 mW; 300 MHz; 90 ps; CMOS technology; DPLL; chip area; digital phase-locked loop; dual modulus frequency divider; fractional frequency synthesizer; jitter; phase frequency acquisition mode; CMOS technology; Clocks; Digital control; Digital-controlled oscillators; Energy consumption; Frequency conversion; Frequency synthesizers; Jitter; Phase locked loops; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2003 International Symposium on

ISSN

1524-766X

Print_ISBN

0-7803-7765-6

Type

conf

DOI

10.1109/VTSA.2003.1252575

Filename

1252575