DocumentCode
2395030
Title
Low power SoC project in STARC
Author
Ishibashi, Koichiro ; Yamashita, Takahiro
Author_Institution
Dept. of Design Technol. Dev., Semicond. Technol. Acad. Res. Center, Yokohama, Japan
fYear
2003
fDate
6-8 Oct. 2003
Firstpage
180
Lastpage
183
Abstract
Low power SoC technology, which realizes ubiquitous computing era, is investigated. Low voltage operation of 0.5V for logic and memory IPs and 1.0V operation for analog IP are target techniques. Such low voltage logic, memory and analog IPs are to be implemented in a single chip to realize super low power SoC.
Keywords
CMOS analogue integrated circuits; CMOS logic circuits; CMOS memory circuits; system-on-chip; 0.5 V; 1 V; STARC; analog IP; logic IP; low power SoC technology; memory IP; target techniques; CMOS technology; Central Processing Unit; Digital circuits; Digital signal processing chips; Large scale integration; Leakage current; Logic; Low voltage; Memory management; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2003 International Symposium on
ISSN
1524-766X
Print_ISBN
0-7803-7765-6
Type
conf
DOI
10.1109/VTSA.2003.1252582
Filename
1252582
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