DocumentCode
2395842
Title
A scalable architecture system for automatic target recognition
Author
David, Philip ; Emmerman, Philip ; Ho, Sean
Author_Institution
Army Res. Lab., Adelphi, MD, USA
fYear
1994
fDate
30 Oct-3 Nov 1994
Firstpage
414
Lastpage
420
Abstract
Automatic target recognition (ATR) is a very difficult problem due to the variety of conditions under which an ATR system may be required to operate. Because the number of operations required to execute a particular ATR algorithm can vary greatly from one scenario to another; a fixed hardware and software architecture will usually not be able to execute a given ATR algorithm in all required scenarios within some given real-time constraints. A solution to this problem is to use a scalable architecture. The hardware and software of such an architecture can easily be scaled to meet the processing requirements of a particular scenario. This paper describes a scalable architecture system which we have developed that implements a real-time ATR algorithm
Keywords
military computing; parallel algorithms; parallel architectures; pattern recognition; real-time systems; ATR; C40 processors; automatic target recognition; real-time ATR algorithm; real-time constraints; scalable architecture; software architecture; Computer architecture; Digital signal processing; Hardware; Infrared detectors; Laboratories; Layout; Signal processing algorithms; Software algorithms; Software architecture; Target recognition;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital Avionics Systems Conference, 1994. 13th DASC., AIAA/IEEE
Conference_Location
Phoenix, AZ
Print_ISBN
0-7803-2425-0
Type
conf
DOI
10.1109/DASC.1994.369448
Filename
369448
Link To Document