Analysis and FPGA implementation of fast Ordering Detection Algorithm for V-BLAST system

This paper firstly presents a fast ordering V-BLAST detection algorithm based on QR decomposition which is implemented in hardware platform of 4G TDD MIMO- OFDM wireless transmission demonstration system developed by our research team. This algorithm avoids the iteration for pseudo inverse in traditional Golden ZF-SIC by a new sorting scheme and achieves the same performance as traditional Golden ZF-SIC at lower complexity. An effective and resource-saving FPGA architecture for this algorithm is proposed including logic implementation, pipeline design and fixed point programming. A novel method of LUT division design -“multi-LUTs” strategy is proposed to increase the performance of LUT divider which also consumes less resource and increases processing speed comparing with IP core integrated in Xilinx FPGA. At last simulation is presented to validate the design and statistics on resource utilization of such a scheme in Virtex-5 XC5VSX95T FPGA of Xilinx Company is given while the scheme is verified on 4G TDD system hardware platform which achieves steady and high throughput (1 gbps peak rate) in real-time system.