A module-sliced high yield WSI memory system

Low yield is one of the practical difficulties in the design of WSI systems, such as array processors or WSI memories. The conventional row-column memory cells organization is not suitable for WSI memory systems due to the long signal delay on a wafer and a much more complicate procedure for replacing a defect row or column of memory cell. To alleviate these difficulties, a module-sliced WSI memory system is proposed for high yield WSI memory systems. The basic unit of the WSI memory system is a module which consists of a memory bank, a module comparator, a module register, and a row-column decoder. The WSI memory system is organized in a two level row/column structure. The first level is a two dimensional mesh with the basic unit of a module. Within each module, i.e. the second level, the memory bank is organized in a conventional rows and columns of memory cells