DocumentCode
2397541
Title
An evaluation of defect and fault tolerant signal routing strategies for WASP devices
Author
Hussaini, M.B. ; Bolouri, H. ; Lea, Robert Mike
Author_Institution
Brunel Univ., Uxbridge, UK
fYear
1995
fDate
18-20 Jan 1995
Firstpage
277
Lastpage
287
Abstract
The paper presents an investigation into two defect and fault tolerant signal routing strategies for WASP devices. The success rate of each strategy in establishing good signal routing connections, for a complete 32-bit WASP bus structure in the presence of randomly distributed defects is investigated using Monte Carlo simulations. The most efficient, as well as defect and fault tolerant, of the two strategies is then identified
Keywords
Monte Carlo methods; associative processing; fault tolerant computing; microprocessor chips; network routing; parallel machines; wafer-scale integration; 32 bit; Monte Carlo simulation; WASP bus structure; WASP devices; WSI associative string processor; defect tolerant signal routing strategies; fault tolerant signal routing strategies; randomly distributed defects; Application specific processors; Assembly; Communication system control; Concurrent computing; Fault diagnosis; Fault tolerance; Manufacturing; Prototypes; Routing; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-2467-6
Type
conf
DOI
10.1109/ICWSI.1995.515462
Filename
515462
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