• DocumentCode
    2397622
  • Title

    The impact of floorplanning on the yield of fault-tolerant ICs

  • Author

    Koren, Zahava ; Koren, Israel

  • Author_Institution
    Dept. of Ind. Eng. & Oper. Res., Massachusetts Univ., Amherst, MA, USA
  • fYear
    1995
  • fDate
    18-20 Jan 1995
  • Firstpage
    329
  • Lastpage
    338
  • Abstract
    Until now, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips
  • Keywords
    VLSI; integrated circuit layout; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; VLSI design; fault-tolerant ICs; floorplanning; large area VLSI chips; yield model; Circuit faults; Computer industry; Design engineering; Fault tolerance; Niobium; Operations research; Performance evaluation; Redundancy; System testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-2467-6
  • Type

    conf

  • DOI
    10.1109/ICWSI.1995.515467
  • Filename
    515467
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2397622