Evaluation of I/sub DDT? testing for CMOS domino circuits

We propose a method for testing domino CMOS circuits using the transient power supply current, i_DDT. The method is based on properly setting the primary inputs of the circuit under test, switching the clock signal, and monitoring the peak magnitude of I_DDT. If the magnitude of the current pulse lies outside a predetermined range, a defect is inferred. We target resistive open defects that can either cause the circuit to fail, or introduce unacceptable delay and hence result in degraded circuit performance. Previous results show the potential of i_DDT to detect such faults for small domino circuits (3-10 domino gates). In this paper, we show that this method is also applicable to larger circuits, by selecting the inputs in such a way to minimize the switching activity in the circuit, except at the fault location, and by canceling the effect of the capacitive coupling current component. Fault simulation results on benchmark CMOS domino circuits show a high rate of detection for resistive open faults that cannot be otherwise detected using traditional voltage or I_DDQ testing, even in the presence of process variations