Simulation modeling and testing of SRAMs using dynamic current

We present an i_DDT-based methodology for testing embedded SRAMs. The targeted defects are opens, shorts and pattern sensitive faults. We present the test algorithm and we assess its fault coverage by performing fault simulations for a large on a number of defects introduced into a memory circuit. We build and fabricate a test chip consisting of a defect free circuit and defected memory circuits and we assess the effectiveness of the algorithm by performing physical measurements on the chip. Also, we study the effect of process variation on the test algorithm