Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications

Author

Hong, Sangjin ; Kim, Suhwan ; Papaefthymiou, Marios C. ; Stark, Wayne E.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Volume

1

fYear

1999

fDate

1999

Firstpage

313

Abstract

Large fixed-throughput fast Fourier transform (FFT) modules are used in multi-carrier spread spectrum receiver design for demodulation and synchronization. The power dissipation of an FFT module depends highly on the number of processing units and their interconnect topology. This paper analyzes the energy dissipation and complexity of a pipelined parallel FFT architecture. Optimum design choices are presented for the degree of spatial parallelism and temporal multiplexing. Simulation results are obtained using EPOCH and HSPICE with 0.35 μm standard CMOS technology

Keywords

CMOS digital integrated circuits; OFDM modulation; VLSI; demodulation; fast Fourier transforms; microprocessor chips; mobile radio; pipeline processing; spread spectrum communication; synchronisation; transceivers; 0.35 micron; CMOS technology; EPOCH; HSPICE; demodulation; energy dissipation; interconnect topology; low energy wireless communication applications; multi-carrier spread spectrum receiver design; pipelined VLSI FFT architectures; pipelined parallel FFT architecture; power dissipation; power-complexity analysis; processing units; spatial parallelism; synchronization; temporal multiplexing; CMOS technology; Capacitance; Computer architecture; Frequency; Integrated circuit interconnections; Parallel processing; Power dissipation; Throughput; Very large scale integration; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. 42nd Midwest Symposium on

Conference_Location

Las Cruces, NM

Print_ISBN

0-7803-5491-5

Type

conf

DOI

10.1109/MWSCAS.1999.867269

Filename

867269