DC bus ripple minimization in cascaded H-bridge multilevel converters under staircase modulation

Cascade connected H bridge multilevel converters are becoming an attractive topology for very high power applications. Due the single phase loading of the individual bridges, the DC link capacitors required in these converters are faced with a heavy stress. The problem is particularly acute with stair-case type modulation strategies. This paper presents an approach for equalizing the power drawn from each H bridge within less than one cycle period with the aim of reducing capacitor sizing. The presented approach is based on rearranging the switching strategies focusing on the redundancies in synthesizing output voltage of H bridge multilevel converters. The proposed approach also holds nearly the same degree of freedom in selecting conduction angles and attains similar levels of harmonic performance as with conventional switching angle selection approaches. The analysis presented in this paper is also confirmed by simulation.