Sub-gate-delay edge-control of a clock signal using DLLs and ΣΔ modulation techniques

Many high-speed communication applications require precise edge-control for establishing ideal sampling conditions. A delay-locked loop (DLL) is often used to phase shift the incoming reference clock signal in increments of the propagation delay of a single inverter circuit. Through the application of sigma-delta modulation techniques, this paper will demonstrate how a DLL can be used to provide precise edge-control with sub-gate-delay resolution.